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1994 data sheet mos integrated circuit m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f description the m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, and 78018f are the products in the m pd78018f subseries within the 78k/0 series. compared with the older m pd78014 subseries, this subseries operates at lower voltage and provides a fuller set of rom and ram variations. a one-time prom or eprom product m pd78p018f capable of operating in the same power supply voltage range as of the mask rom product and other development tools are also provided. functions are described in detail in the following user's manual, which should be read when carring out design work. m pd78018f, 78018fy subseries user's manual : u10659e 78k/0 series users manual C instruction : u12326e features large on-chip rom & ram 8-bit single-chip microcontroller item program data memory memory internal high- internal buffer ram package product name (rom) speed ram expanded ram m pd78011f 8k bytes 512 bytes C 32 bytes 64-pin plastic shrink dip (750 mil) m pd78012f 16k bytes 64-pin plastic qfp (14 14 mm) m pd78013f 24k bytes 1024 bytes 64-pin plastic lqfp (12 12 mm) m pd78014f 32k bytes m pd78015f 40k bytes 512 bytes m pd78016f 48k bytes m pd78018f 60k bytes 1024 bytes external memory expansion space : 64k bytes minimum instruction execution time can be varied from high-speed (0.4 m s) to ultra-low-speed (122 m s) i/o ports: 53 (n-ch open-drain : 4) 8-bit resolution a/d converter : 8 channels serial interface : 2 channels timer : 5 channels supply voltage : v dd = 1.8 to 5.5 v application fields cellular phone, pager, vcr, audio, camera, home appliances, etc the information in this document is subject to change without notice. the mark shows major revised points. document no. u10280ej2v1ds00 (2nd edition) date published june 1998 n cp(k) printed in japan
2 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f ordering information part number package m pd78011fcw- 64-pin plastic shrink dip (750 mil) m pd78011fgc- -ab8 64-pin plastic qfp (14 14 mm) m pd78011fgk- -8a8 64-pin plastic lqfp (12 12 mm) m pd78012fcw- 64-pin plastic shrink dip (750 mil) m pd78012fgc- -ab8 64-pin plastic qfp (14 14 mm) m pd78012fgk- -8a8 64-pin plastic lqfp (12 12 mm) m pd78013fcw- 64-pin plastic shrink dip (750 mil) m pd78013fgc- -ab8 64-pin plastic qfp (14 14 mm) m pd78013fgk- -8a8 64-pin plastic lqfp (12 12 mm) m pd78014fcw- 64-pin plastic shrink dip (750 mil) m pd78014fgc- -ab8 64-pin plastic qfp (14 14 mm) m pd78014fgk- -8a8 64-pin plastic lqfp (12 12 mm) m pd78015fcw- 64-pin plastic shrink dip (750 mil) m pd78015fgc- -ab8 64-pin plastic qfp (14 14 mm) m pd78015fgk- -8a8 64-pin plastic lqfp (12 12 mm) m pd78016fcw- 64-pin plastic shrink dip (750 mil) m pd78016fgc- -ab8 64-pin plastic qfp (14 14 mm) m pd78016fgk- -8a8 64-pin plastic lqfp (12 12 mm) m pd78018fcw- 64-pin plastic shrink dip (750 mil) m pd78018fgc- -ab8 64-pin plastic qfp (14 14 mm) m pd78018fgk- -8a8 64-pin plastic lqfp (12 12 mm) remark indicates a rom code suffix.
3 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 78k/0 series development the following shows the products organized according to usage. the names in the parallelograms are subseries names. 64-pin 64-pin 64-pin 64-pin 80-pin 80-pin emi-noise reduced version of the pd78054 uart and d/a converter were enhanced to the pd78014 and i/o was enhanced pd78054 pd78054y pd78058f pd78058fy pd780034 pd780024 pd780964 pd780924 pd780034y pd780024y m m m m m m m m m m 64-pin a/d converter of the pd780024 was enhanced serial i/o of the pd78018f was added and emi-noise was reduced. on-chip inverter control circuit and uart. emi-noise was reduced. m m m m a/d converter of the pd780924 was enhanced m pd78044f pd78044h 80-pin 80-pin pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y pd78098 80-pin pd78p0914 64-pin 78k/0 series an n-ch open drain i/o was added to the pd78044f, display output total: 34 basic subseries for driving fip, display output total: 34 lcd drive the sio of the pd78064 was enhanced, and rom, ram capacity increased emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart iebus tm supported an iebus controller was added to the pd78054 lv on-chip pwm output, lv digital code decoder, and hsync counter m m m m m m m m m m m m m m m m pd78083 pd78002 pd78002y pd780001 pd78014 pd78014y pd78018f pd78018fy low-voltage (1.8 v) operation version of the pd78014, with larger selection of rom and ram capacities an a/d converter and 16-bit timer were added to the pd78002 an a/d converter was added to the pd78002 basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) m m m m m m m m 42/44-pin 64-pin 64-pin 64-pin 64-pin pd78014h m emi-noise reduced version of pd78018f m m pd780058 pd780058y note m m 80-pin serial i/o of the pd78054 was enhanced and emi-noise was reduced. 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. a timer was added to the pd78054 and external interface was enhanced rom-less version of the pd78078 pd78070a pd78070ay m pd78078 pd78078y pd780018ay m m m m m 100-pin serial i/o of the pd78078y was enhanced and the function is limited. m m 100-pin control pd78075b pd78075by m m emi-noise reduced version of pd78078 m inverter control pd780228 100-pin the i/o and fip c/d of the pd78044h were enhanced, display output total: 48 m m m pd780208 100-pin fip tm drive the i/o and fip c/d of the pd78044f were enhanced, display output total: 53 m m pd780208 m pd78098b emi-noise reduced version of the pd78098 m 80-pin m meter control pd780973 on-chip controller/driver for automobile meters m 80-pin note under planning
4 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f the following lists the main functional differences between subseries products. function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd min. external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control m pd78075b 32k-40k 4ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 88 1.8 v m pd78078 48k-60k m pd78070a C 61 2.7 v m pd780058 24k-60k 2ch 2ch 3ch (time division uart: 1ch) 68 1.8 v m pd78058f 48k-60k 3ch (uart: 1ch) 69 2.7 v m pd78054 16k-60k 2.0 v m pd780034 8k-32k C 8ch C 3ch (uart: 1ch, 51 1.8 v m pd780024 8ch C time division 3-wire: 1ch) m pd78014h 2ch 53 1.8 v m pd78018f 8k-60k m pd78014 8k-32k 2.7 v m pd780001 8k C C 1ch 39 C m pd78002 8k-16k 1ch C 53 m pd78083 C 8ch 1ch (uart: 1ch) 33 1.8 v C inverter m pd780964 8k-32k 3ch note C 1ch C 8ch C 2ch (uart: 2ch) 47 2.7 v control m pd780924 8ch C fip m pd780208 32k-60k 2ch 1ch 1ch 1ch 8ch C C 2ch 74 2.7 v C drive m pd780228 48k-60k 3ch C C 1ch 72 4.5 v m pd78044h 32k-48k 2ch 1ch 1ch 68 2.7 v m pd78044f 16k-40k 2ch lcd m pd780308 48k-60k 2ch 1ch 1ch 1ch 8ch C C 3ch (time division uart: 1ch) 57 2.0 v C drive m pd78064b 32k 2ch (uart: 1ch) m pd78064 16k-32k iebus m pd78098 40k-60k 2ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 69 2.7 v supported m pd78098b 32k-60k meter control m pd780973 24k-32k 3ch 1ch 1ch 1ch 5ch C C 2ch (uart: 1ch) 56 4.5 v C lv m pd78p0914 32k 6ch C C 1ch 8ch C C 2ch 54 4.5 v note 10-bit timer: 1 channel
5 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 8k bytes 16k bytes 24k bytes 32k bytes 40k bytes 48k bytes 60k bytes 32 bytes 64k bytes 8 bits 32 registers (8 bits 8 registers 4 banks) on-chip minimum instruction execution time cycle modification function 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (at 10.0 mhz operation) 122 m s (at 32.768 khz operation) ? 16-bit operation ? multiplication/division (8 bits 8 bits,16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd correction, etc. total : 53 ? cmos input : 0 2 ? cmos i/o : 47 ? n-channel open-drain i/o (15 v withstand voltage) : 0 4 ? 8-bit resolution 8 channels ? operable over a wide power supply voltage range: av dd = 1.8 to 5.5 v ? 3-wire serial i/o/sbi/2-wire serial i/o mode selectable: 1 channel ? 3-wire mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel 3 (14-bit pwm output 1) 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz (at main system clock: 10.0 mhz operation), 32.768 khz (at subsystem clock: 32.768 khz operation) 2.4 khz, 4.9 khz, 9.8 khz (at main system clock: 10.0 mhz operation) internal : 8 external : 4 internal : 1 1 internal memory memory space general-purpose registers minimum instruction execution time overview of function (1/2) instruction set i/o ports a/d converter serial interface timer timer output clock output product name rom high-speed ram expanded ram buffer ram when main system clock selected when subsystem clock selected buzzer output vectored interrupt sources 512 bytes 1024 bytes 512 bytes 1024 bytes m pd78011f m pd78012f m pd78013f m pd78014f m pd78015f m pd78016f m pd78018f item maskable non-maskable software
6 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f overview of function (2/2) test input supply voltage operating ambient temperature package product name m pd78011f m pd78012f m pd78013f m pd78014f m pd78015f m pd78016f m pd78018f item internal : 1 external : 1 v dd = 1.8 to 5.5 v ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp (14 14 mm) ? 64-pin plastic lqfp (12 12 mm) t a = C40 to +85 c
7 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f table of contents 1. pin configuration (top view) ................................................................................................. ...... 8 2. block diagram ................................................................................................................ ................... 11 3. pin functions ................................................................................................................ ...................... 12 3.1 port pins ................................................................................................................... ..................................... 12 3.2 pins other than port pins ................................................................................................... ................... 13 3.3 pin i/o circuits and recommended connection of unused pins ............................................. 15 4. memory space ................................................................................................................. ................... 17 5. periphel hardware function features ................................................................................ 19 5.1 ports ....................................................................................................................... ........................................ 19 5.2 clock generator ............................................................................................................. .......................... 20 5.3 timer/event counter ......................................................................................................... ....................... 21 5.4 clock output control circuit ................................................................................................ ............ 23 5.5 buzzer output control circuit ............................................................................................... ............ 23 5.6 a/d converter ............................................................................................................... ............................... 24 5.7 serial interfaces ........................................................................................................... ........................... 24 6. interrupt functions and test functions .............................................................................. 26 6.1 interrupt functions ......................................................................................................... ........................ 26 6.2 test functions .............................................................................................................. .............................. 29 7. external device expansion functions .................................................................................... 30 8. standby functions ............................................................................................................ .............. 30 9. reset functions .............................................................................................................. .................. 30 10. instruction set ............................................................................................................. .................... 31 11. electrical specifications ................................................................................................... ......... 34 12. characteristic curve (reference values) ........................................................................... 61 13. package drawings ............................................................................................................ ............... 62 14. recommended soldering conditions ....................................................................................... 65 appendix a. development tools ................................................................................................ ...... 68 appendix b. related documents ................................................................................................ ...... 70
8 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 64-pin plastic shrink dip (750 mil) m pd78011fcw- , 78012fcw- , 78013fcw- , m pd78014fcw- , 78015fcw- , 78016fcw- , m pd78018fcw- 1. pin configuration (top view) cautions 1. always connect the ic (internally connected) pin to v ss directly. 2. always connect the av dd pin to v dd . 3. always connect the av ss pin to v ss . 1 p20/si1 2 p21/so1 3 p22/sck1 4 p23/stb 5 p24/busy 6 p25/si0/sb0 7 p26/so0/sb1 8 p27/sck0 9 p30/to0 10 p31/to1 11 p32/to2 12 p33/ti1 13 p34/ti2 14 p35/pcl 15 p36/buz 16 p37 17 v ss 18 p40/ad0 19 p41/ad1 20 p42/ad2 21 p43/ad3 22 p44/ad4 23 p45/ad5 24 p46/ad6 25 p47/ad7 26 p50/a8 27 p51/a9 28 p52/a10 29 p53/a11 30 p54/a12 31 p55/a13 32 v ss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 av ref av dd p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ss p04/xt1 xt2 ic x1 x2 v dd p03/intp3 p02/intp2 p01/intp1 p00/intp0/ti0 reset p67/astb p66/wait p65/wr p64/rd p63 p62 p61 p60 p57/a15 p56/a14
9 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 64-pin plastic qfp (14 14 mm) m pd78011fgc- -ab8, 78012fgc- -ab8, 78013fgc- -ab8, m pd78014fgc- -ab8, 78015fgc- -ab8, 78016fgc- -ab8, m pd78018fgc- -ab8 64-pin plastic lqfp (12 12 mm) m pd78011fgk- -8a8, 78012fgk- -8a8, 78013fgk- -8a8, m pd78014fgk- -8a8, 78015fgk- -8a8, 78016fgk- -8a8, m pd78018fgk- -8a8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p11/ani1 p10/ani0 av ss p04/xt1 xt2 ic x1 x2 v dd p03/intp3 p02/intp2 p01/intp1 p00/intp0/ti0 reset p67/astb p66/wait p37 v ss p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p27/sck0 p26/so0/sb1 p25/si0/sb0 p24/busy p23/stb p22/sck1 p21/so1 p20/si1 av ref av dd p17/ani7 p16/ani6 p15/ani5 p14/ani4 p13/ani3 p12/ani2 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd p65/wr cautions 1. always connect the ic (internally connected) pin to v ss directly. 2. always connect the av dd pin to v dd . 3. always connect the av ss pin to v ss .
10 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f a8 to a15 : address bus ad0 to ad7 : address/data bus ani0 to ani7 : analog input astb : address strobe av dd : analog power supply av ref : analog reference voltage av ss : analog ground busy : busy buz : buzzer clock ic : internally connected intp0 to intp3 : interrupt from peripherals p00 to p04 : port0 p10 to p17 : port1 p20 to p27 : port2 p30 to p37 : port3 p40 to p47 : port4 p50 to p57 : port5 p60 to p67 : port6 pcl : programmable clock rd : read strobe reset : reset sb0, sb1 : serial bus sck0, sck1 : serial clock si0, si1 : serial input so0, so1 : serial output stb : strobe ti0 to ti2 : timer input to0 to to2 : timer output v dd : power supply v ss : ground wait : wait wr : write strobe x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock)
11 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 2. block diagram 16-bit timer/ event counter 8-bit timer/ event counter 1 8-bit timer/ event counter 2 watchdog timer serial interface 0 serial interface 1 a/d converter interrupt control watch timer buzzer output clock output control to0/p30 ti0/intp0/p00 to1/p31 ti1/p33 to2/p32 ti2/p34 si0/sb0/p25 so0/sb1/p26 sck0/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 ani0/p10 to ani7/p17 av dd av ss av ref intp0/p00 to intp3/p03 buz/p36 pcl/p35 78k/0 cpu core rom ram v dd v ss ic ( v pp ) port0 port1 port2 port3 port4 port5 port6 external access system control p00 p01 to p03 p04 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 ad0/p40 to ad7/p47 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1 xt2 remarks 1. internal rom & ram capacity varies depending on the product. 2. ( ) : m pd78p018f
12 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f input input/ output input/ output input/ output input p00 p01 p02 p03 p04 note 1 p10 to p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34 p35 p36 p37 p40 to p47 3. pin functions 3.1 port pins (1/2) input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used in software. input input intp0/ti0 intp1 intp2 intp3 xt1 ani0 to ani7 si1 so1 sck1 stb busy si0/sb0 so0/sb1 sck0 to0 to1 to2 ti1 ti2 pcl buz ad0 to ad7 input input/ output input/ output input input input input only input only port 2 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used in software. port 1 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used in software. note 2 port 0 5-bit i/o port port 3 8-bit input/output port. input/output can be specified in 1-bit units. when used as an input port, on-chip pull-up resistor can be used in software. port 4 8-bit input/output port. input/output can be specified in 8-bit unit. when used as an input port, on-chip pull-up resistor can be used in software. test input flag (krif) is set to 1 by falling edge detection. notes 1. when using the p04/xt1 pins as an input port, set 1 to bit 6 (frc) of the processor clock control register (pcc). do not use the on-chip feedback register of the subsystem clock oscillator. 2. when using the p10/ani0 to p17/ani7 pins as the a/d converter analog input, on-chip pull-up resistor is automatically unused. pin name i/o function on reset dual- function pin input
13 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 3.1 port pins (2/2) input/ output p50 to p57 input/ output p60 p61 p62 p63 p64 p65 p66 p67 input input a8 to a15 port 5 8-bit input/output port. led can be driven directly. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used in software. port 6 8-bit input/output port. input/output can be specified bit-wise. when used as an input port, on-chip pull-up resistor can be used in soft- ware. n-ch open-drain input/output port. on-chip pull-up resistor can be specified by mask option. led can be driven directly. rd wr wait astb pin name i/o function on reset dual- function pin 3.2 pins other than port pins (1/2) intp0 intp1 intp2 intp3 si0 si1 so0 so1 sb0 sb1 sck0 sck1 stb busy input input output input /output input /output output input external interrupt request input by which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. input input input input p00/ti0 p01 p02 p03 p25/sb0 p20 p26/sb1 p21 p25/si0 p26/so0 p27 p22 p23 p24 falling edge detection external interrupt request input. serial interface serial data input. serial interface serial data output. serial interface serial data input/output. serial interface serial clock input/output. serial interface automatic transmit/receive strobe output. serial interface automatic transmit/receive busy input. input input input pin name i/o function on reset dual- function pin
14 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f ti0 ti1 ti2 to0 to1 to2 pcl buz ad0 to ad7 a8 to a15 rd wr wait astb input output external count clock input to 16-bit timer (tm0). external count clock input to 8-bit timer (tm1). external count clock input to 8-bit timer (tm2). 16-bit timer (tm0) output (shared as 14-bit pwm output). output input /output clock output (for main system clock, subsystem clock trimming). buzzer output. low-order address/data bus at external memory expansion. high-order address bus at external memory expansion. external memory read operation strobe signal output. external memory write operation strobe signal output. wait insertion at external memory access. output strobe output which latches the address information output at port 4 and port 5 to access external memory. output output input output 3.2 pins other than port pins (2/2) a/d converter analog input. a/d converter reference voltage input. a/d converter analog power supply. connected to v dd . a/d converter ground potential. connected to v ss . system reset input. main system clock oscillation crystal connection. subsystem clock oscillation crystal connection. positive power supply. ground potential. internal connection. connected to v ss directly. ani0 to ani7 av ref av dd av ss reset x1 x2 xt1 xt2 v dd v ss ic input input input input input input input input input input input input input input input input 8-bit timer (tm1) output. p00/intp0 p33 p34 p30 p31 p32 p35 p36 p40 to p47 p50 to p57 p64 p65 p66 p67 p10 to p17 p04 pin name i/o function on reset dual- function pin 8-bit timer (tm2) output.
15 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, refer to figure 3-1 . table 3-1. input/output circuit type of each pin 2 8-a 16 11 8-a 5-a 8-a 5-a 8-a 10-a 5-a 8-a 5-a 5-e 5-a 13-b 5-a 2 16 pin name i/o recommended connection when not used input/output circuit type p00/intp0/ti0 p01/intp1 p02/intp2 p03/intp3 p04/xt1 p10/ani0 to p17/ani7 p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0 p26/so0/sb1 p27/sck0 p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p37 p40/ad0 to p47/ad7 p50/a8 to p57/a15 p60 to p63 p64/rd p65/wr p66/wait p67/astb reset xt2 av ref av dd av ss ic input input/output input input/output input connected to v ss . individually connected to v ss via resistor. connected to v dd or v ss . individually connected to v dd or v ss via resisitor. individually connected to v dd via resistor. individually connected to v dd or v ss via resistor. individually connected to v dd via resistor. individually connected to v dd or v ss via resistor. leave open. connected to v ss . connected to v dd . connected to v ss . connected to v ss directly.
16 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f figure 3-1. pin input/output circuits type 11 type 10-a type 13-b type 16 type 8-a type 5-a type 2 type 5-e pull-up enable data output disable v p-ch n-ch p-ch in / out dd v dd pull-up enable data output disable v p-ch n-ch p-ch in / out dd v dd input enable pull-up enable data output disable v p-ch n-ch p-ch in / out dd v dd in schmitt-triggered input with hysteresis characteristic pull-up enable data output disable in / out n-ch v ref input enable pull-up enable data output disable v p-ch n-ch p-ch in / out dd v dd open drain xt1 (threshold voltage) v p-ch n-ch p-ch dd v p-ch + comparator dd data output disable n-ch in / out v dd v dd rd mask option middle-high voltage input buffer feedback cut-off xt2 p-ch p-ch
17 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 1fffh 3fffh 5fffh 7fffh 4. memory space the memory maps of the m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, and 78018f are shown in figure 4-1 and 4-2. figure 4-1. memory map ( m pd78011f, 78012f, 78013f, 78014f) note intermal rom and internal high-speed ram capacities vary depending on the product (refer to the table below). m pd78011f m pd78012f m pd78013f m pd78014f intenal rom end address nnnnh product name internal high-speed ram start address mmmmh fd00h fb00h ffffh ff00h feffh mmmmh mmmmh ?1 fee0h fedfh fae0h fadfh fac0h fabfh fa80h fa7fh nnnnh + 1 nnnnh 0000h nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h special function registers (sfr) 256 8 bits general-purpose registers 32 8 bits internal high-speed ram note use prohibited buffer ram 32 8 bits use prohibited external memory program area callf entry area program area callt table area vector table area program memory space data memory space internal rom note
18 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f figure 4-2. memory map ( m pd78015f, 78016f, 78018f) ffffh fa7fh ff00h feffh f800h f7ffh kkkkh kkkkh ?1 nnnnh + 1 mmmmh mmmmh? fee0h fedfh fae0h fadfh fac0h fabfh fa80h nnnnh 0000h nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h special function registers (sfr) 256 8 bits general-purpose registers 32 8 bits internal high-speed ram note use prohibited buffer ram 32 8 bits use prohibited program area callf entry area program area callt table area vector table area use prohibited internal expanded ram note external memory program memory space data memory space internal rom note note intermal rom, internal high-speed ram, and internal expanded ram capacities vary depending on the product (refer to the table below). 9fffh bfffh efffh m pd78015f m pd78016f m pd78018f intenal rom end address nnnnh product name internal high-speed ram start address mmmmh fb00h internal expanded ram start address kkkkh f600h f400h
19 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 5. peripheral hardware function features 5.1 ports p00, p04 p01 to p03 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p63 p64 to p67 port 0 port 1 port 2 port 3 port 4 port 5 port 6 dedicated input port input/output ports. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used in software. input/output ports. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used in software. input/output ports. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used in software. input/output ports. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used in software. input/output ports. input/output can be specified in 8-bit units. when used as an input port, pull-up resistor can be used in software. test input flag (krif) is set to 1 by falling edge detection. input/output ports. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used in software. led can be driven directly. n-ch open-drain input/output port. input/output can be specified bit-wise. on-chip pull-up resistor can be specified by mask option. led can be driven directly. input/output ports. input/output can be specified bit-wise. when used as an input port, pull-up resistor can be used in software. function port name table 5-1. functions of ports pin name the i/o port has the following three types ? cmos input (p00, p04) : 2 ? cmos input/output (p01 to p03, port 1 to port 5, p64 to p67) : 47 ? n-ch open-drain input/output(15v withstand voltage) (p60 to p63) : 4 total : 53
20 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 5.2 clock generator figure 5-1. clock generator block diagram prescaler prescaler xt1/p04 xt2 x1 x2 stop f x 2 3 f x 2 4 f x 2 2 f x 2 f x f xt clock to peripheral hardware subsystem clock oscillator main system clock oscillator standby control circuit wait control circuit cpu clock (f cpu ) intp0 sampling clock there are two types of clock generator: main system clock and subsystem clock. the minimum instruction exection time can be changed. ? 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s (main system clock: at 10.0 mhz operation) ? 122 m s (subsystem clock: at 32.768 khz operation) watch timer clock output function selector
21 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f operation interval timer 1 channel 2 channels 1 channel 1 channel mode externanal event counter 1 channel 2 channels C C functions timer output 1 output 2 outputs C C pwm output 1 output C C C pulse width mesurement 1 input C C C sqare wave output 1 output 2 outputs C C interrupt request 2 2 1 1 test input C C 1 input C 5.3 timer/event counter the following five channels are incorporated in the timer/event counter. ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 2 channels ? watch timer : 1 channel ? watchdog timer : 1 channel table 5-2. operation of timer/event counter 16-bit timer/event counter watch timer watchdog timer 8-bit timer/event counter figure 5-2. 16-bit timer/enent counter block diagram f x /2 2 f x /2 f x /2 3 ti0/intp0/p00 clear selector output control circuit inttm0 to0/p30 intp0 match selector internal bus pwm pulse output control circuit edge detector 16-bit compare register (cr00) 16-bit timer register (tm0) 16-bit capture register (cr01) internal bus
22 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f inttm3 intwt 5-bit counter prescaler selector selector selector selector ti1/p33 f x /2 12 f x /2 2 to f x /2 10 ti2/p34 f x /2 12 f x /2 2 to f x /2 10 figure 5-3. 8-bit timer/enent counter block diagram internal bus 8-bit compare register (cr10) 8-bit timer register 1 (tm1) clear output control circuit output control circuit intim1 to2/p32 inttm2 to1/p31 clear match selector 8-bit compare register (cr20) 8-bit timer register 2 (tm2) internal bus selector selector selector selector figure 5-4. watch timer block diagram f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 f x /2 8 f x t f w 2 14 f w 2 13 f w
23 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f figure 5-5. watchdog timer block diagram f x /2 10 f x /2 11 f x /2 12 5.5 buzzer output control circuit the clock with the following frequencies can be output for buzzer output. ? 2.4 khz/4.9 khz/9.8 khz (main system clock: at 10.0 mhz operation) figure 5-7. buzzer output control block diagram 5.4 clock output control circuit the clock with the following frequencies can be output for clock output. ? 39.1 khz/78.1 khz/156 khz/313 khz/625 khz/1.25 mhz (main system clock: at 10.0 mhz operation) ? 32.768 khz (subsystem clock: at 32.768 khz operation) figure 5-6. clock output control block diagram f xt f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x 2 5 f x 2 6 f x 2 7 f x 2 8 f x 2 9 f x 2 12 f x 2 10 f x 2 4 control circuit 8-bit counter prescaler intwdt non-maskable interrupt request intwdt maskable interrupt request reset selector selector synchronization circuit output control circuit pcl/p35 selector output control circuit buz/p36
24 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 5.6 a/d converter the a/d converter has on-chip eight 8-bit resolution channels. there are the following two method to start a/d conversion. ? hardware starting ? software starting figure 5-8. a/d converter block diagram 5.7 serial interfaces there are two on-chip clocked serial interfaces as follows. ? serial interface channel 0 ? serial interface channel 1 function serial interface channel 0 serial interface channel 1 3-wire serial i/o mode o (msb/lsb-first switchable) o (msb/lsb-first switchable) 3-wire serial i/o mode with automatic data transmit/ C o (msb/lsb-first switchable) receive function sbi (serial bus interface) mode o (msb-first) C 2-wire serial i/o mode o (msb-first) C table 5-3. type and function of serial interface tap selector intad av dd intp3 internal bus av ref av ss a/d conversion result register (adcr) control circuit succesive approxmation register (sar) falling edge detector ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 intp3/p03 selector sample & hold circuit voltage comparator series resistor string
25 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f figure 5-9. serial interface channel 0 block diagram si0/sb0/p25 so0/sb1/p26 sck0/p27 intcsi0 to2 f x /2 2 to f x/ 2 9 busy/acknowlede output circuit output latch serial i/o shift register 0 (sio0) internal bus interrupt request signal generator serial clock counter bus release/command/ acknowledge detection circuit serial clock control circuit selector selector selector figure 5-10. serial interface channel 1 block diagram internal bus interrupt request signal generator handshake control circuit buffer ram serial clock control circuit selector serial clock counter serial i/o shift register 1 (sio0) automatic data transmit/ receive address pointer (adtp) si1/p20 so1/p21 stb/p23 busy/p24 sck/p22 intcsi1 f x /2 2 to f x /2 9 to2
26 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f default interrupt source internal/ vector table basic interrupt type priority note 1 name trigger external address configuratin type note 2 non-maskable CCC intwdt watchdog timer overflow (with watchdog internal 0004h (a) timer mode 1 selected) maskable 0 intwdt watchdog timer overflow (with interval (b) timer mode selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h (d) 3 intp2 000ah 4 intp3 000ch 5 intcsi0 serial interface channel 0 transfer end internal 000eh (b) 6 intcsi1 serial interface channel 1 transfer end 0010h 7 inttm3 reference time interval signal from 0012h watch timer 8 inttm0 16 bit timer/event counter match signal 0014h generation 9 inttm1 8-bit timer/event counter 1 match signal 0016h generation 10 inttm2 8-bit timer/event counter 2 match signal 0018h generation 11 intad a/d converter conversion end 001ah software CCC brk brk instruction execution CCC 003eh (e) 6. interrupt functions and test functions 6.1 interrupt functions table 6-1. interrupt source list notes 1. the default pririty is the priority applicable when more than one maskable interrupt request is generated. 0 is the highest priority and 11, the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) on the next page. there are interrupt functions, 14 sources of three different kinds, as shown below. ? non-maskable : 1 ? maskable : 12 ? software : 1
27 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f figure 6-1. basic interrupt function configuration (1/2) (a) internal non-maskable interrupt (c) external maskable interrupt (intp0) (b) internal maskable interrupt internal bus priority control circuit vector table address generator standby release signal interrupt request mk internal bus ie pr isp if priority control circuit vector table address generator standby release signal interrupt request mk ie pr isp if priority control circuit vector table address generator sampling clock select register (scs) external interrupt mode register (intm0) edge detector sampling clock internal bus standby release signal interrupt request
28 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f (d) external maskable interrupt (except intp0) figure 6-1. basic interrupt function configuration (2/2) (e) software interrupt if : interrupt request flag ie : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority spcification flag mk ie pr isp if priority control circuit vector table address generator external interrupt mode register (intm0) edge detector internal bus standby release signal interrupt request priority control circuit vector table address generator internal bus interrupt request
29 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 6.2 test functions there are two test functions as shown in table 6-2. figure 6-2. test function basic configuration if : test input flag mk : test mask flag table 6-2. test source list test source internal/external name trigger intwt watch timer overflow internal intpt4 port 4 falling edge detection external mk internal bus if standby release signal test input
30 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 7. external device expansion functions the external device expansion function is used to connect external devices to areas other than the internal rom, ram and sfr. ports 4 to 6 are used for connection with external devices. 8. standby functions there are the following two standby functions to reduce the current dissipation. ? halt mode : the cpu operating clock is stopped. the average consumption current can be reduced by intermittent operation in combination with the normal operat ing mode. ? stop mode : the main system clock oscillation is stopped. the whole operation by the main system clock is stopped, so that the system operates withultra-low power consumption using only the subsystem clock. figure 8-1. standby functions note the power consumption can be reduced by stopping the main system clock. when the cpu is operating on the subsystem clock, set the bit 7 (mcc) of the processor clock control register (pcc) to stop the main system clock. the stop instruction cannot be used. caution when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program by the program. 9. reset functions there are the following two reset methods. ? external reset input by reset pin. ? internal reset by watchdog timer runaway time detection. main system clock operation stop mode (main system clock oscillation stopped) halt mode (clock supply to cpu is stopped, oscillation) subsystem clock operation note halt mode note (clock supply to cpu is stopped, oscillation) interrupt request interrupt request interrupt request halt instruction halt instruction stop instruction css=1 css=0
31 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 2nd operand [hl+byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl+b] $adder16 1 none 1st operand [hl+c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov sadder mov mov dbnz inc add dec addc sub subc and or xor cmp !adder16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl+byte] mov [hl+b] [hl+c] x mulu c divuw note except r=a 10. instruction set (1) 8-bit instruction mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz
32 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f (2) 16-bit instruction movw, xchw addw, subw, cmpw, push, pop, incw, decw 2nd operand 1st operand #byte ax rp saddrp !addr16 sp none ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw, decw push, pop sfrp movw movw sadderp movw movw !adder16 movw sp movw movw note only when rp=bc, de, hl. (3) bit manipulation instruction mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr 2nd operand 1st operand a.bit sfr.bit saddr.bit pws.bit [hl].bit cy $addr16 none a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 note
33 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f (4) call instruction/branch instruction call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz 2nd operand 1st operand ax !addr16 !addr11 [addr5] $addr16 basic instruction br call, br callf callt br, bc, bnc, bz, bnz compound instruction bt,bf, btclr, dbnz (5) other instruction adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
34 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 11. electrical specifications absolute maximum ratings (t a = 25 c) note rms should be calculated as follows: [rms] = [peak value] ? duty caution product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. that is, the absolute maximuam ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. parameter symbol test conditions rating unit supply voltage v dd C0.3 to +7.0 v av dd C0.3 to v dd + 0.3 v av ref C0.3 to v dd + 0.3 v av ss C0.3 to +0.3 v input voltage p00 to p04, p10 to p17, p20 to p27, p30 to p37 C0.3 to v dd + 0.3 v p40 top47, p50 to p57, p64 to p67, x1, x2, xt2 v i2 p60 to p67 open-drain C0.3 to +16 v output voltage v o C0.3 to v dd + 0.3 v analog input p10 to p17 analog input pin av ss C 0.3 to av ref + 0.3 v voltage output 1 pin C10 ma current high i oh p10 to p17, p20 to p27, p30 to p37 total C15 ma p01 to p03, p40 to p47, p50 to p57, p60 to p67 total C15 ma output 1 pin peak value 30 ma current low rms 15 ma p40 to p47, p50 to p55 total peak value 100 ma rms 70 ma p01 to p03, p56, p57, peak value 100 ma p60 to p67 total rms 70 ma p01 to p03, peak value 50 ma p64 to p67 total rms 20 ma p10 to p17, p20 to p27, p30 to p37 peak value 50 ma total rms 20 ma operating ambient C40 to +85 c temperature storage C65 to +150 c temperature v i1 v an i ol note t a t stg
35 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f parameter symbol test conditions min. typ. max. unit input capacitance c in f = 1 mhz unmeasured pins returned to 0 v 15 pf i/o capacitance p01 to p03, p10 to p17, f = 1 mhz unmeasured p20 to p27, p30 top37, 15 pf c io pins returned to 0 v p40 top47, p50 to p57, p64 to p67 p60 to p63 20 pf unit mhz ms mhz ms mhz ns 2.7 v v dd 5.5 v 1 10 1.8 v v dd < 2.7 v 1 5 v dd = 4.5 to 5.5 v 10 30 capacitance ( t a = 25 c, v dd = v ss = 0 v ) remark the characteristics of a dual-function pin and a port pin are the same unless specified otherwise. main system clock oscillation circuit characteristics ( t a = C40 to +85 c, v dd = 1.8 to 5.5 v) resonator ceramic resonator crystal resonator external clock m pd74hcu04 recommended circuit parameter oscillator frequency (f x ) note 1 oscillation stabilization time note 2 oscillator frequency (f x ) note 1 oscillation stabilization time note 2 x1 input frequency (f x ) note 1 x1 input high/low level width (t xh , t xl ) typ. max. test conditions after v dd reaches oscil- lator voltage range min. notes 1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wiring the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. l wiring should be as short as possible. l wiring should not cross other signal lines. l wiring should not be placed close to a varying high current. l the potential of the oscillator capacitor ground should be the same as v ss . l do not ground wiring to a ground pattern in which a high current flows. l do not fetch a signal from the oscillator. 2. when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. min. 2.7 v v dd 5.5 v 1 10 1.8 v v dd < 2.7 v 1 5 4 1.0 10.0 45 500 x1 x2 c2 c1 r1 v ss x1 x2 c2 c1 v ss x1 x2
36 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f subsystem clock oscillation circuit characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillator voltage min. min. 32 32 5 typ. 32.768 1.2 max. 35 2 10 100 15 unit khz s khz m s resonator crystal resonator external clock test conditions v dd = 4.5 to 5.5 v parameter oscillator frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high/low level width (t xth , t xtl ) cautions 1. when using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. l wiring should be as short as possible. l wiring should not cross other signal lines. l wiring should not be placed close to a varying high current. l the potential of the oscillator capacitor ground should be the same as v ss . l do not ground wiring to a ground pattern in which a high current flows. l do not fetch a signal from the oscillator. 2. the subsystem clock oscillation circuit is a circuit with a low amplification level,more prone to misoperation due to noise than the main system clock. particular care is therefore required with the wiring method when the subsystem clock is used. recommended circuit xt1 xt2 c4 c3 r2 v ss xt1 xt2
37 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f recommended oscillation circuit constant recommended oscillation circuit constant differs depending on the model. (1) m pd78011f, 78012f, 78013f, 78014f (a) main system clock: ceramic resonator (t a = C45 to +85 c) frequency recommended oscillation oscillation manufacturer product name (mhz) circuit constant voltage range c1 (pf) c2 (pf) min. (v) max. (v) tdk corp. ccr4.19mc3 4.19 built-in built-in 1.8 5.5 fcr4.19mc5 4.19 built-in built-in 1.8 5.5 ccr5.00mc3 5.00 built-in built-in 1.8 5.5 fcr5.00mc5 5.00 built-in built-in 1.8 5.5 ccr8.38mc 8.00 built-in built-in 2.7 5.5 fcr8.38mc5 8.00 built-in built-in 2.7 5.5 ccr10.00mc 10.00 built-in built-in 2.7 5.5 fcr10.00mc5 10.00 built-in built-in 2.7 5.5 murata mfg. co. ltd. csa4.19mg 4.19 30 30 1.8 5.5 cst4.19mgw 4.19 built-in built-in 1.8 5.5 csa5.00mg 5.00 30 30 1.8 5.5 cst5.00mgw 5.00 built-in built-in 1.8 5.5 csa8.38mtz 8.38 30 30 2.7 5.5 cst8.38mtw 8.38 built-in built-in 2.7 5.5 csa10.00mtz 10.00 30 30 2.7 5.5 cst10.00mtw 10.00 built-in built-in 2.7 5.5 (b) main system clock: ceramic resonator (t a = C20 to +80 c) frequency recommended oscillation oscillation manufacturer product name (mhz) circuit constant voltage range c1 (pf) c2 (pf) min. (v) max. (v) kyocera corp. pbrc5.00a 5.00 33 33 1.8 5.5 pbrc5.00b 5.00 built-in built-in 1.8 5.5 kbr-5.00msa 5.00 33 33 1.8 5.5 kbr-5.00mks 5.00 built-in built-in 1.8 5.5 kbr-8m 8.00 33 33 2.7 5.5 kbr-10m 10.00 33 33 2.7 5.5 caution the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee the accuracy of the oscillation frequency. if the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. for this, it is necessary to directly contact manufacturer of the resonator being used.
38 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f (b) main system clock: ceramic resonator (t a = C20 to +80 c) frequency recommended oscillation oscillation manufacturer product name (mhz) circuit constant voltage range c1 (pf) c2 (pf) min. (v) max. (v) kyocera corp. pbrc5.00a 5.00 33 33 1.8 5.5 pbrc5.00b 5.00 built - in built - in 1.8 5.5 kbr-5.00msa 5.00 33 33 1.8 5.5 kbr-5.00mks 5.00 built - in built - in 1.8 5.5 kbr-8m 8.00 33 33 2.7 5.5 kbr-10m 10.00 33 33 2.7 5.5 caution the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee the accuracy of the oscillation frequency. if the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. for this, it is necessary to directly contact manufacturer of the resonator being used. (2) m pd78015f, 78016f (a) main system clock: ceramic resonator (t a = C45 to +85 c) frequency recommended oscillation oscillation manufacturer product name (mhz) circuit constant voltage range c1 (pf) c2 (pf) r1 (k w ) min. (v) max. (v) tdk corp. csb1000j 1.00 100 100 5.6 1.8 6.0 csa2.00mg040 2.00 100 100 0 1.8 6.0 cst2.00mg040 2.00 built - in built - in 0 1.8 6.0 csa4.00mg040 4.00 100 100 0 1.8 6.0 cst4.00mgw040 4.00 built - in built - in 0 1.8 6.0 csa6.00mg 6.00 30 30 0 1.8 6.0 cst6.00mgw 6.00 built - in built - in 0 1.8 6.0 csa10.0mtz 10.0 30 30 0 1.8 6.0 cst10.0mtw 10.0 built - in built - in 0 1.8 6.0 murata mfg. co. ltd. csa6.00mg040 6.00 100 100 0 2.7 6.0 (emi noise reduced cst6.00mgw040 6.00 built - in built - in 0 2.7 6.0 products) csa10.0mtz040 10.0 100 100 0 2.7 6.0 cst10.0mtw040 10.0 built - in built - in 0 2.7 6.0 tdk corp. fcr4.0mc5 4.0 built - in built - in 2.2 1.8 6.0 fcr10.0mc 10.0 built - in built - in 1.0 1.8 6.0
39 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f (3) m pd78018f (a) main system clock: ceramic resonator (t a = C40 to +85 c) frequency recommended oscillation oscillation manufacturer product name (mhz) circuit constant voltage range c1 (pf) c2 (pf) min. (v) max. (v) tdk corp. ccr4.0mc3 4.00 built - in built - in 1.8 5.5 fcr4.0mc5 4.00 built - in built - in 1.8 5.5 ccr8.0mc5 8.00 built - in built - in 2.7 5.5 fcr8.0mc 8.00 built - in built - in 2.7 5.5 ccr10.0mc5 10.0 built - in built - in 2.7 5.5 fcr10.0mc 10.0 built - in built - in 2.7 5.5 murata mfg. co. ltd. csa4.0mg 4.00 30 30 1.8 5.5 cst4.0mgw 4.00 built - in built - in 1.8 5.5 csa8.0mtz 8.00 30 30 2.7 5.5 cst8.0mtw 8.00 built - in built - in 2.7 5.5 (b) main system clock: ceramic resonator (t a = C20 to +80 c) frequency recommended oscillation oscillation manufacturer product name (mhz) circuit constant voltage range c1 (pf) c2 (pf) min. (v) max. (v) kyocera corp. fbrc4.00a 4.00 33 33 1.8 5.5 fbrc4.00b 4.00 built - in built - in 1.8 5.5 kbr-4.00msb 4.00 33 33 1.8 5.5 kbr-4.00mkc 4.00 built - in built - in 1.8 5.5 kbr-8m 8.00 33 33 2.7 5.5 kbr-10m 10.00 33 33 2.7 5.5 caution the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee the accuracy of the oscillation frequency. if the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. for this, it is necessary to directly contact manufacturer of the resonator being used.
40 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f parameter symbol test conditions min. typ. max. unit input voltage v ih1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0.7 v dd v dd v high p35 to p37, p40 to p47, p50 to p57, p64 to 67 v ih2 p00 to p03, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0.8 v dd v dd v p33, p34, reset 0.85 v dd v dd v v ih3 p60 to p63 v dd = 2.7 to 5.5 v 0.7 v dd 15 v (n-ch open-drain) 0.8 v dd 15 v v ih4 x1, x2 v dd = 2.7 to 5.5 v v dd C 0.5 v dd v v dd C 0.2 v dd v v ih5 xt1/p04, xt2 4.5 v v dd 5.5 v 0.8 v dd v dd v 2.7 v v dd < 4.5 v 0.9 v dd v dd v 1.8 v v dd < 2.7 v note 0.9 v dd v dd v input voltage v il1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0 0.3 v dd v low p35 to p37, p40 to p47, p50 to p57, p64 to 67 v il2 p00 to p03, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0 0.2 v dd v p33, p34, reset 0 0.15 v dd v v il3 p60 to p63 4.5 v v dd 5.5 v 0 0.3 v dd v 2.7 v v dd < 4.5 v 0 0.2 v dd v 0 0.1 v dd v v il4 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v 0 0.2 v v il5 xt1/p04, xt2 4.5 v v dd 5.5 v 0 0.2 v dd v 2.7 v v dd < 4.5 v 0 0.1 v dd v 1.8 v v dd < 2.7 v note 0 0.1 v dd v output v oh1 v dd = 4.5 to 5.5 v, i oh = C1 ma v dd C 1.0 v voltage high i oh = C100 m av dd C 0.5 v output v ol1 p50 to p57, p60 to p63 v dd = 4.5 to 5.5 v, 0.4 2.0 v voltage low i ol = 15 ma p01 to p03, p10 to p17, p20 to p27 v dd = 4.5 to 5.5 v, 0.4 v p30 to p37, p40 to p47, p64 to p67 i ol = 1.6 ma v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, open-drain 0.2 v dd v pulled-up (r = 1 k w ) v ol3 i ol = 400 m a 0.5 v dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) 0.8 v dd v dd v note when using xt1/p04 as p04, input the inverse of p04 to xt2 using an inverter. remark the characteristics of a dual-function pin and a port pin are the same unless specified otherwise. 0 0.2 v dd v
41 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f parameter symbol test conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p03, p10 to p17, 3 m a current high p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, reset i lih2 x1, x2, xt1/p04, xt2 20 m a i lih3 v in = 15 v p60 to p63 80 m a input leakege i lil1 v in = 0 v p00 to p03, p10 to p17, C3 m a current low p20 to p27, p30 to p37, p40 to p47, p50 to p57, p60 to p67, reset i lil2 x1, x2, xt1/p04, xt2 C20 m a i lil3 p60 to p63 C3 note m a output leakage i loh1 v out = v dd 3 m a current high output leakage i lol v out = 0 v C3 m a current low mask option r1 v in = 0 v, p60 to p63 20 40 90 k w pull-up resister software r2 v in = 0 v, p01 to p03, p10 to p17, p20 to p27, p30 to p37, 15 40 90 k w pull-up resister p40 to p47, p50 to p57, p60 to p67 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) note for p60 to p63, if pull-up resistor is not provided (specifiable by mask option) a low-level input leak current of C200 m a (max.) flows only during the 3 clocks (no-wait time) after an instruction has been executed to read out port 6 (p6) or port mode register 6 (pm6). outside the period of 3 clocks following execution a read-out instruction, the current is C3 m a (max.). remark the characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
42 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f parameter symbol test conditions min. typ. max. unit supply i dd1 10.00 mhz crystal v dd = 5.0 v 10 % note 2 9.0 18.0 ma current note 1 oscillation operation mode v dd = 3.0 v 10 % note 3 1.3 2.6 ma i dd2 10.00 mhz crystal v dd = 5.0 v 10 % note 2 2.4 4.8 ma oscillation halt mode v dd = 3.0 v 10 % note 3 1.2 2.4 ma i dd3 32.768 khz crystal v dd = 5.0 v 10 % 60 120 m a oscillation operation mode note 4 v dd = 3.0 v 10 % 35 70 m a v dd = 2.0 v 10 % 24 48 m a i dd4 32.768 khz crystal v dd = 5.0 v 10 % 25 50 m a oscillation halt mode note 4 v dd = 3.0 v 10 % 5 15 m a v dd = 2.0 v 10 % 2 10 m a i dd5 xt1 = v dd v dd = 5.0 v 10 % 1 30 m a stop mode when using feedback v dd = 3.0 v 10 % 0.5 10 m a resistor v dd = 2.0 v 10 % 0.3 10 m a i dd6 xt1 = v dd v dd = 5.0 v 10 % 0.1 30 m a stop mode when not using v dd = 3.0 v 10 % 0.05 10 m a feedback resistor v dd = 2.0 v 10 % 0.05 10 m a dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. this current excludes the av ref current, port current, and current which flows in the built-in pull-down resistor. 2. when operating at high-speed mode (when the processor clock control register (pcc) is set to 00h) 3. when operating at low-speed mode (when the pcc is set to 04h) 4. when main system clock stopped.
43 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f parameter symbol test conditions min. typ. max. unit cycle time t cy operating on main system clock 3.5 v v dd 5.5 v 0.4 64 m s (min. instruction 2.7 v v dd < 3.5 v 0.8 64 m s execution time) 1.8 v v dd < 2.7 v 2.0 64 m s operating on subsystem clock 40 122 125 m s ti0 input t tih0 3.5 v v dd 5.5 v 2/f sam + 0.1 note m s frequency t til0 2.7 v v dd < 3.5 v 2/f sam + 0.2 note m s 1.8 v v dd < 2.7 v 2/f sam + 0.5 note m s ti1, ti2 input f ti1 v dd = 4.5 to 5.5 v 0 4 mhz frequency 0 275 khz ti1, ti2 input high/low-level width interrupt t inth intp0 3.5 v v dd 5.5 v 2/f sam + 0.1 note m s request input t intl 2.7 v v dd < 3.5 v 2/f sam + 0.2 note m s high/low-level 1.8 v v dd < 2.7 v 2/f sam + 0.5 note m s width intp1 to intp3, kr0 to kr7 v dd = 2.7 to 5.5 v 10 m s 20 m s reset low t rsl v dd = 2.7 to 5.5 v 10 m s level width 20 m s ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) note in combination with bits 0 (scs0) and 1 (scs1) of sampling clock select register (scs), selection of fsam is possible between fx/2 n+1 , fx/64 and fx/128 (when n= 0 to 4). t til1 1.8 m s t tih1 v dd = 4.5 to 5.5 v 100 ns
44 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f t cy vs v dd (at main system clock operation) 60.0 5.0 1.0 0.5 0.1 supply voltage v dd [v] cycle time t cy [ s] 0 10.0 1.0 2.0 3.0 4.0 5.0 6.0 1.8 3.5 5.5 2.7 operation guaranteed range m
45 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f parameter symbol test conditions min. max. unit astb high-level width t asth 0.5t cy ns address setup time t ads 0.5t cy C 30 ns address hold time t adh 50 ns data input time from address t add1 (2.5 + 2n) t cy C 50 ns t add2 (3 + 2n) t cy C 100 ns data input time from rd t rdd1 (1 + 2n) t cy C 25 ns t rdd2 (2.5 + 2n) t cy C 100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.5 + 2n) t cy C 20 ns t rdl2 (2.5 + 2n) t cy C 20 ns wait input time from rd t rdwt1 0.5t cy ns t rdwt2 1.5t cy ns wait input time from wr t wrwt 0.5t cy ns wait low-level width t wtl (0.5 + 2n) t cy + 10 (2 + 2n) t cy ns write data setup time t wds 100 ns write data hold time t wdh load resistor 3 5 k w 20 ns wr low-level width t wrl1 (2.5 + 2n) t cy C 20 ns rd delay time from astb t astrd 0.5t cy C 30 ns wr delay time from astb t astwr 1.5t cy C 30 ns astb - delay time from t rdast t cy C 10 t cy + 40 ns rd - in external fetch address hold time from t rdadh t cy t cy + 50 ns rd - in external fetch write data output time from rd - t rdwd v dd = 4.5 to 5.5 v 0.5t cy + 5 0.5t cy + 30 ns 0.5t cy + 15 0.5t cy + 90 ns write data output time from wr t wrwd v dd = 4.5 to 5.5 v 5 30 ns 15 90 ns address hold time from wr - t wradh v dd = 4.5 to 5.5 v t cy t cy + 60 ns t cy t cy + 100 ns rd - delay time from wait - t wtrd 0.5t cy 2.5t cy + 80 ns wr - delay time from wait - t wtwr 0.5t cy 2.5t cy + 80 ns (2) read/write operation (t a = C40 to +85 c, v dd = 2.7 to 5.5 v) remarks 1. t cy = t cy /4 2. n indicates number of waits.
46 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy2 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high/low-level t kh2 4.5 v v dd 5.5 v 400 ns width t kl2 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns si0 setup time t sik2 v dd = 2.0 to 5.5 v 100 ns (to sck0 - ) 150 ns si0 hold time t ksi2 400 ns (from sck0 - ) so0 output delay time t kso2 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns from sck0 500 ns sck0 rise, fall time t r2 when external device 160 ns t f2 expansion function is used when external when 16-bit timer 700 ns device expansion output function is function is not used used when 16-bit timer 1000 ns output function is not used (3) serial interface (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy1 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high/low-level t kh1 v dd = 4.5 to 5.5 v t kcy1 /2 C 50 ns width t kl1 t kcy1 /2 C 100 ns si0 setup time t sik1 4.5 v v dd 5.5 v 100 ns (to sck0 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si0 hold time t ksi1 400 ns (from sck0 - ) so0 output delay time t kso1 c = 100 pf note 300 ns from sck0 note c is the load capacitance of sck0 and so0 output line. (ii) 3-wire serial i/o mode (sck0... external clock input) note c is the load capacitance of so0 output line.
47 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy3 4.5 v v dd 5.5 v 800 ns 2.0 v v dd < 4.5 v 3200 ns 4800 ns sck0 high/low-level t kh3 v dd = 4.5 to 6.0 v t kcy3 /2 C 50 ns width t kl3 t kcy3 /2 C 150 ns sb0, sb1 setup time t sik3 4.5 v v dd 5.5 v 100 ns (to sck0 -) 2.0 v v dd < 4.5 v 300 ns 400 ns sb0, sb1 hold time t ksi3 t kcy3 /2 ns (from sck0 - ) sb0, sb1output delay t kso3 r = 1 k w ,v dd = 4.5 to 5.5 v 0 250 ns time from sck0 c = 100 pf note 0 1000 ns sb0, sb1 from sck0 - t ksb t kcy3 ns sck0 from sb0, sb1 t sbk t kcy3 ns sb0, sb1 high-level t sbh t kcy3 ns width sb0, sb1 low-level t sbl t kcy3 ns width (iii) sbi mode (sck0... internal clock output) note r and c are the load resistors and load capacitance of the sb0, sb1 and sck0 output line.
48 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy4 4.5 v v dd 5.5 v 800 ns 2.0 v v dd < 4.5 v 3200 ns 4800 ns sck0 high/low-level t kh4 4.5 v v dd 5.5 v 400 ns width t kl4 2.0 v v dd < 4.5 v 1600 ns 2400 ns sb0, sb1 setup time t sik4 4.5 v v dd 5.5 v 100 ns (to sck0 -) 2.0 v v dd < 4.5 v 300 ns 400 ns sb0, sb1 hold time t ksi4 t kcy4 /2 ns (from sck0 - ) sb0, sb1 output delay t kso4 r = 1 k w ,v dd = 4.5 to 5.5 v 0 300 ns time from sck0 c = 100 pf note 0 1000 ns sb0, sb1 from sck0 - t ksb t kcy4 ns sck0 from sb0, sb1 t sbk t kcy4 ns sb0, sb1 high-level t sbh t kcy4 ns width sb0, sb1 low-level t sbl t kcy4 ns width sck0 rise, fall time t r4 when external device 160 ns t f4 expansion function is used when external when 16-bit timer 700 ns device expansion output function is function is not used used when 16-bit timer 1000 ns output function is not used (iv) sbi mode (sck0... external clock input) note r and c are the load resistors and load capacitance of the sb0 and sb1 output line.
49 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f (v) 2-wire serial i/o mode (sck0... internal clock output) note r and c are the load resistors and load capacitance of the sck0, sb0 and sb1 output line. parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy5 r = 1 k w , 2.7 v v dd 5.5 v 1600 ns c = 100 pf note 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high-level width t kh5 v dd = 2.7 to 5.5 v t kcy5 /2 C 160 ns t kcy5 /2 C 190 ns sck0 low-level width t kl5 v dd = 4.5 to 5.5 v t kcy5 /2 C 50 ns t kcy5 /2 C 100 ns sb0, sb1 setup time t sik5 4.5 v v dd 5.5 v 300 ns (to sck0 -) 2.7 v v dd < 4.5 v 350 ns 2.0 v v dd < 2.7 v 400 ns 500 ns sb0, sb1 hold time t ksi5 600 ns (from sck0 - ) sb0, sb1 output delay t kso5 0 300 ns time from sck0
50 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f parameter symbol test conditions min. typ. max. unit sck0 cycle time t kcy6 2.7 v v dd 5.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high-level width t kh6 2.7 v v dd 5.5 v 650 ns 2.0 v v dd < 2.7 v 1300 ns 2100 ns sck0 low-level width t kl6 2.7 v v dd 5.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns sb0, sb1 setup time t sik6 v dd = 2.0 to 5.5 v 100 ns (to sck0 -) 150 ns sb0, sb1 hold time t ksi6 t kcy6 /2 ns (from sck0 - ) sb0, sb1 output delay t kso6 r = 1 k w , 4.5 v v dd 5.5 v 0 300 ns time from sck0 c = 100 pf note 2.0 v v dd < 4.5 v 0 500 ns 0 800 ns sck0 rise, fall time t r6 when external device 160 ns t f6 expansion function is used when external when 16-bit timer 700 ns device expansion output function is function is not used used when 16-bit timer 1000 ns output function is not used (vi) 2-wire serial i/o mode (sck0... external clock input) note r and c are the load resistors and load capacitance of the sb0 and sb1 output line.
51 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy8 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high/low-level t kh8 4.5 v v dd 5.5 v 400 ns width t kl8 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns si1 setup time t sik8 v dd = 2.0 to 5.5 v 100 ns (to sck1 - ) 150 ns si1 hold time t ksi8 400 ns (from sck1 - ) so0 output delay time t kso8 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns from sck1 500 ns sck1 rise, fall time t r8 when external device 160 ns t f8 expansion function is used when external when 16-bit timer 700 ns device expansion output function is function is not used used when 16-bit timer 1000 ns output function is not used (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1... internal clock output) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy7 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high/low-level t kh7 v dd = 4.5 to 5.5 v t kcy7 /2 C 50 ns width t kl7 t kcy7 /2 C 100 ns si1 setup time t sik7 4.5 v v dd 5.5 v 100 ns (to sck1 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si1 hold time t ksi7 400 ns (from sck1 - ) so1 output delay time t kso7 c = 100 pf note 300 ns from sck1 note c is the load capacitance of sck1 and so1 output line. (ii) 3-wire serial i/o mode (sck1... external clock input) note c is the load capacitance of so1 output line.
52 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy9 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high/low-level t kh9 v dd = 4.5 to 5.5 v t kcy9 /2 C 50 ns width t kl9 t kcy9 /2 C 100 ns si1 setup time t sik9 4.5 v v dd 5.5 v 100 ns (to sck1 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si1 hold time t ksi9 400 ns (from sck1 - ) so1 output delay time t kso9 c = 100 pf note 300 ns from sck1 stb - from sck1 - t sbd t kcy9 /2 C 100 t kcy9 /2 + 100 ns strobe signal t sbw 2.7 v v dd 5.5 v t kcy9 C 30 t kcy9 + 30 ns high-level width 2.0 v v dd < 2.7 v t kcy9 C 60 t kcy9 + 60 ns t kcy9 C 90 t kcy9 + 90 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 4.5 v v dd 5.5 v 100 ns (from busy signal 2.7 v v dd < 4.5 v 150 ns detection timing) 2.0 v v dd < 2.7 v 200 ns 300 ns sck1 from busy t sps 2t kcy9 ns inactive (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1... internal clock output) note c is the load capacitance of sck1 and so1 output line.
53 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1... external clock input) parameter symbol test conditions min. typ. max. unit sck1 cycle time t kcy10 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high/low-level t kh10 , 4.5 v v dd 5.5 v 400 ns width t kl10 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns si1 setup time t sik10 v dd = 2.0 to 5.5 v 100 ns (to sck1 - ) 150 ns si1 hold time t ksi10 400 ns (from sck1 - ) so1 output delay time t kso10 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns from sck1 500 ns sck1 rise, fall time t r10 , t f10 when external device expansion 160 ns function is used when external device expansion 1000 ns function is not used note c is the load capacitance of the so1 output line.
54 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f ac timing test point (excluding x1, xt1 input) ti timing clock timing 0.8 v dd 0.2 v dd test points 0.8 v dd 0.2 v dd ti0 t til0 t tih0 ti1,ti2 1/f ti1 t til1 t tih1 x1 input v ih4 (min.) v il4 (max.) 1/f x t xl t xh xt1 input v ih5 (min.) v il5 (max.) 1/f xt t xtl t xth
55 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f read/write operation external fetch (no wait): external fetch (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address lower 8-bit address t add1 h i -z t ads t asth t adh t rdd1 operation code t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 ad0 to ad7 astb rd higher 8-bit address t add1 h i -z t ads t asth t adh t rdd1 operation code t rdadh t rdast t astrd t rdl1 t rdh wait t rdwt1 t wtl t wtrd lower 8-bit address
56 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f external data access (no wait): a8 to a15 ad0 to ad7 astb rd higher 8-bit address t add2 h i -z t ads t asth t adh t rdd2 read data t astrd t rdwd wr t astwr write data h i -z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 h i -z lower 8-bit address external data access (wait insertion): a8 to a15 ad0 to ad7 astb rd higher 8-bit address t add2 t ads t asth t adh t rdd2 read data t astrd wr t astwr write data h i -z t wdh t wradh t wds t wrwd t wrl1 t rdh t rdl2 t rdwt2 t wtl t wrwt t wtl t wtwr t wtrd wait t rdwd h i -z h i -z lower 8-bit address
57 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f sbi mode (bus release signal transfer): sbi mode (command signal transfer): serial transfer timing 3-wire serial i/o mode: sck0 sb0, sb1 t ksb t sbl t sbh t sbk t kcy3, 4 t kl3, 4 t kh3, 4 t sik3, 4 t ksi3, 4 t kso3, 4 t r4 t f4 sck0 sb0, sb1 t ksb t sbk t kcy3, 4 t kl3, 4 t kh3, 4 t sik3, 4 t ksi3, 4 t kso3, 4 t r4 t f4 si0,si1 so0,so1 m = 1, 2, 7, 8 n = 2, 8 t kcym t klm t khm t sikm t ksim input data t ksom output data t fn t rn sck0,sck1
58 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 2-wire serial i/o mode: note the signal is not actually driven low here; it is shown as such to indicate the timing. sck0 sb0, sb1 t kcy5,6 t kl5,6 t kh5,6 t r6 t f6 t kso5,6 t sik5,6 t ksi5,6 so1 sck1 si1 stb d2 d1 d0 d2 d1 d0 t sik9,10 t ksi9,10 t kso9,10 t kh9,10 t f10 t r10 t kl9,10 t kcy9,10 t sbw t sbd d7 d7 3-wire serial i/o mode with automatic transmit/receive function: sck1 busy 7 8 910 10 + n t bys t byh t sps 1 (active high) note note note 3-wire serial i/o mode with automatic transmit/receive function (busy processing):
59 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f data retention timing (stop mode release by reset) parameter symbol test conditions min. typ. max. unit resolution 8 8 8 bit overall error note 2.7 v av ref av dd 0.6 % 1.8 v av ref < 2.7 v 1.4 % conversion time t conv 2.0 v av dd 5.5 v 19.1 200 m s 1.8 v av dd < 2.0 v 38.2 200 m s sampling time t samp 24/f x m s analog input voltage v ian av ss av ref v reference voltage av ref 1.8 av dd v av ref resistance r airef 414 k w a/d converter characteristics (t a = C40 to +85 c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) note overall error excluding quantization error ( 1/2 lsb). it is indicated as a ratio to the full-scale value. data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) parameter symbol test conditions min. typ. max. unit data retention supply v dddr 1.8 5.5 v voltage data retention supply i dddr v dddr = 1.8 v 0.1 10 m a current subsystem clock stop and feed- back resister disconnected release signal set time t srel 0 m s oscillation stabilization t wait release by reset 2 18 /f x ms wait time release by interrupt request note ms note in combination with bit 0 to bit 2 (osts0 to osts2) of oscillation stabilization time select register (osts), selection of 2 13 /f x and 2 15 /f x to 2 18 /f x is possible. v dd stop instruction execution reset v dddr internal reset operation halt mode operating mode t wait t srel data retension mode stop mode
60 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f data retention timing (standby release signal : stop mode release by interrupt request signal) v dd stop instruction execition standby release signal (interrupt request) v dddr halt mode operating mode t srel t wait data retension mode stop mode interrupt request input timing reset input timing t intl t inth t intl intp0 to intp2 intp3 t rsl reset
61 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 12. characteristic curve (reference values) (t a = 25 c) pcc = 00h pcc = 01h pcc = 02h pcc = 03h pcc = 04h pcc = 30h pcc = b0h f x = 10.0 mhz f xt = 32.768 khz 0 0.001 halt (x1 oscillation, xt1 stop) halt (x1 stop, xt1 oscillation) 12345678 0.005 0.01 0.05 0.1 0.5 1.0 5.0 10.0 i dd vs v dd (main system clock: 10.0 mhz) supply voltage v dd [v] supply current i dd [ma]
62 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 13. package drawings a i j g h f d n m c b m r 64 33 32 1 k l note each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. p64c-70-750a,c-1 item millimeters inches a b c d f g h i j k 58.68 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 n 0~15 0.50?.10 0.9 min. r 2.311 max. 0.070 max. 0.020 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0~15 +0.004 ?.003 0.070 (t.p.) 1) item "k" to center of leads when formed parallel. 2) +0.10 ?.05 +0.004 ?.005 64 pin plastic shrink dip (750 mil) remark dimensions and materials of es products are the same as those of mass-production products.
63 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f remark dimensions and materials of es products are the same as those of mass-production products. n a m f b 48 49 32 k l 64 pin plastic qfp ( 14) 64 1 17 16 33 d c detail of lead end s q 55 p m i h j g p64gc-80-ab8-2 item millimeters inches a b c d f g h i j k l 17.6 0.4 14.0 0.2 1.0 0.35 0.10 0.15 14.0 0.2 0.693 0.016 0.039 0.039 0.006 0.031 (t.p.) 0.551 note m n 0.10 0.15 1.8 0.2 0.8 (t.p.) 0.004 0.006 +0.004 0.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.071 0.008 0.014 0.551 0.8 0.2 0.031 p 2.55 0.100 0.693 0.016 17.6 0.4 1.0 +0.009 0.008 q 0.1 0.1 0.004 0.004 s 2.85 max. 0.112 max. +0.10 0.05 +0.009 0.008 +0.004 0.005 +0.009 0.008
64 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f remark dimensions and materials of es products are the same as those of mass-production products. 64 pin plastic lqfp ( 12) item millimeters inches d f g k i j 1.125 1.125 1.4?.2 0.65 (t.p.) 0.13 14.8?.4 q 0.583?.016 0.044 0.044 0.055?.008 0.005 0.026 (t.p.) p64gk-65-8a8-1 a f note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. c 12.0?.2 0.472 m 0.15 0.006 0.125?.075 0.005?.003 +0.004 ?.003 +0.009 ?.008 a 14.8?.4 0.583?.016 h 0.30?.10 0.012 +0.004 ?.005 l 0.6?.2 0.024 +0.008 ?.009 n 0.10 0.004 p 1.4 0.055 s r 1.7 max. 5 ? 0.067 max. 5 ? +0.10 ?.05 b 12.0?.2 0.472 +0.009 ?.008 m 48 49 32 64 1 17 16 33 b g hi j c d p n l k m detail of lead end s q r
65 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f 14. recommended soldering conditions the m pd78011f/78012f/78013f/78014f/78015f/78016f/78018f should be soldered and mounted under the condi- tions recommended in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact our salespersonnel. table 14-1. surface mounting type soldering conditions (1/2) (1) m pd78011fgc- -ab8: 64-pin plastic qfp (14 14 mm) m pd78012fgc- -ab8: 64-pin plastic qfp (14 14 mm) m pd78013fgc- -ab8: 64-pin plastic qfp (14 14 mm) m pd78014fgc- -ab8: 64-pin plastic qfp (14 14 mm) m pd78015fgc- -ab8: 64-pin plastic qfp (14 14 mm) m pd78016fgc- -ab8: 64-pin plastic qfp (14 14 mm) m pd78018fgc- -ab8: 64-pin plastic qfp (14 14 mm) recommended condition symbol soldering method soldering conditions infrared reflow vps wave soldering partial heating package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), number of times: three times max. package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above), number of times: three times max. solder bath temperature: 260 c max. duration: 10 sec. max. number of times: once preheating temperature: 120 c max. (package surface temperature) pin temperature: 300 c max., duration: 3 sec. max. (per device side) ir35-00-3 vp15-00-3 ws60-00-1 caution use more than one soldering method should be avoided (except in the case of partial heating).
66 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f table 14-1. surface mounting type soldering conditions (2/2) (2) m pd78011fgk- -8a8 : 64-pin plastic lqfp (12 12 mm) m pd78012fgk- -8a8 : 64-pin plastic lqfp (12 12 mm) m pd78013fgk- -8a8 : 64-pin plastic lqfp (12 12 mm) m pd78014fgk- -8a8 : 64-pin plastic lqfp (12 12 mm) m pd78015fgk- -8a8 : 64-pin plastic lqfp (12 12 mm) m pd78016fgk- -8a8 : 64-pin plastic lqfp (12 12 mm) m pd78018fgk- -8a8 : 64-pin plastic lqfp (12 12 mm) recommended condition symbol soldering method soldering conditions infrared reflow vps wave soldering partial heating package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), number of times: twice max., number of days: 7 days note (after that, 125 c prebaking for 10 hours is necessary.) < precautions > (1) start the second reflow after the device temprature by the first reflow returns to normal. (2) flux washing by the water after the first reflow should be avoided. package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above), number of times: twice max., number of days: 7 days note (after that, 125 c prebaking for 10 hours is necessary.) < precautions > (1) start the second reflow after the device temprature by the first reflow returns to normal. (2) flux washing by the water after the first reflow should be avoided. solder bath temperature: 260 c max. duration: 10 sec. max. number of times: once, preheating temperature: 120 c max. (package surface temperature), number of days: 7 days note (after that, 125 c prebaking for 10 hours is necessary.) pin temperature: 300 c max., duration: 3 sec. max. (per device side) ir35-107-2 vp15-107-2 ws60-107-1 note the number of days the device can be stored at 25 c, 65% rh max. after the dry pack has been opend. caution use more than one soldering method should be avoided (except in the case of partial heating).
67 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f table 14-2. insertion type soldering conditions m pd78011fcw- : 64-pin plastic shrink dip (750 mil) m pd78012fcw- : 64-pin plastic shrink dip (750 mil) m pd78013fcw- : 64-pin plastic shrink dip (750 mil) m pd78014fcw- : 64-pin plastic shrink dip (750 mil) m pd78015fcw- : 64-pin plastic shrink dip (750 mil) m pd78016fcw- : 64-pin plastic shrink dip (750 mil) m pd78018fcw- : 64-pin plastic shrink dip (750 mil) soldering method soldering conditions wave soldering (pin only) partial heating solder bath temperature: 260 c max., duration: 10 sec. max. pin temperature: 300 c max., duration: 3 sec. max. (per pin) caution wave soldering is only for the lead part in order that jet solder can not contact with the chip directly.
68 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f appendix a. development tools the following development tools are available for system development using the m pd78018f subseries. language processing software ra78k/0 notes 1, 2, 3, 4 78k/0 series common assembler package cc78k/0 notes 1, 2, 3, 4 78k/0 series common c compiler package df78014 notes 1, 2, 3, 4 device file common to m pd78014 subseries cc78k/0-l notes 1, 2, 3, 4 78k/0 series common c compiler library source file prom writting tools pg-1500 prom programmer pa-78p014cw programmer adapter connected to pg-1500 pa-78p018gc pa-78p018gk pa-78p018kk-s pg-1500 controller notes 1, 2 pg-1500 control program debugging tool ie-78000-r 78k/0 series common in-circuit emulator ie-78000-r-a 78k/0 series common in-circuit emulator (for integrated debugger) ie-78000-r-bk 78k/0 series common break board ie-78014-r-em-a m pd78018f and 78018fy subseries evaluation emulation board (v dd = 3.0 to 6.0 v) ie-78000-r-sv3 interface adapter and cable when an ews is used as the host machine (for ie-78000r-a) ie-70000-98-if-b interface adapter when pc-9800 series (except notebook pc) is used as the host machine (for ie-78000-r-a) ie-70000-98n-if interface adapter and cable when pc-9800 series notebook pc is used as the host machine (for ie-78000-r-a) ie-70000-pc-if-b interface adapter when ibm pc/at tm is used as the host machine (for ie-78000-r-a) ep-78240cw-r emulation probe common to m pd78244 subseries ep-78240gc-r ev-78012gk-r m pd78018f subseries emulation probe ev-9200gc-64 socket to be mounted on target system board created for the 64-pin plastic qfp (gc-ab8 type) tgc-064sbw conversion adapter to be mounted on a target system board made for 64-pin plastic qfp (gk-8a8 type) tgc-100sdw is a product from tokyo eletech corp. (tel (03) 5295-1661) when purchasing this product, please consult with our sales offices. ev-9900 tools for removing m pd78p018fkk-s from ev-9200gc-64 sm78k0 notes 5, 6, 7 78k/0 series common system simulator id78k0 notes 4, 5, 6, 7 ie-78000-r-a integrated dubugger sd78k/0 notes 1, 2 ie-78000-r screen debugger df78014 notes 1, 2, 4, 5, 6, 7 device file common to m pd78014 subseries real-time os rx78k/0 notes 1, 2, 3, 4 78k/0 series real-time os mx78k0 notes 1, 2, 3, 4 78k/0 series os
69 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f fuzzy inference devleopment support system fe9000 note 1 /fe9200 note 6 fuzzy knowledge data creation tool ft9080 note 1 /ft9085 note 2 translator fi78k0 notes 1, 2 fuzzy inference module fd78k0 notes 1, 2 fuzzy inference debugger notes 1. pc-9800 series (ms-dos tm ) based 2. ibm pc/at and compatible (pc dos tm /ibm dos tm /ms-dos) based 3. hp9000 series 300 tm (hp-ux tm ) based 4. hp9000 series 700 tm (hp-ux) based, sparcstation tm (sunos tm ) based, ews4800 series (ews-ux/v) based 5. pc-9800 series (ms-dos + windows tm ) based 6. ibm pc/at and compatible (pc dos/ibm dos/ms-dos + windows) based 7. news tm (news-os tm ) based remarks 1. for development tools manufactured by a third party, refer to the 78k/0 series selection guide (u11126e) . 2. ra78k/0, cc78k/0, sm78k0, id78k0, sd78k/0, and rx78k/0 are used in combination with df78014.
70 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f appendix b. related documents device related documents document name document no. japanese english m pd78018f, 78018fy subseries users manual u10659j u10659e 78k/0 series users manual - instruction u12326j ieu-1372 78k/0 series instruction table u10903j 78k/0 series instruction set u10904j m pd78018f subseries special function register table iem-5594 78k/0 series application note fundamental (i) iea-715 iea-1288 floating-point arithmetic program iea-718 iea-1289 development tools documents (users manual) (1/2) document name document no. japanese english ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 ra78k0 assembler package operation u11802j u11802e assembly language u11801j u11801e structured assembly language u11789j u11789e cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k0 c compiler operation u11517j u11517e language u11518j u11518e cc78k/0 c compiler application note programming know-how eea-618 eea-1208 cc78k series library source file u12322j pg-1500 prom programmer u11940j eeu-1335 pg-1500 controller pc-9800 series (ms-dos) based eeu-704 eeu-1291 pg-1500 controller ibm pc series (pc dos) based eeu-5008 u10540e ie-78000-r u11376j u11376e e-78000-r-a u10057j u10057e ie-78000-r-bk eeu-867 eeu-1427 ie-78014-r-em-a eeu-962 u10418e ep-78240 eeu-986 eeu-1513 ep-78012gk-r eeu-5012 eeu-1538 sm78k0 system simulator reference u10181j u10181e caution the contents of the above related documents are subject to change without notice. the latest documents should be used for designing, etc.
71 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f development tools documents (users manual) (2/2) document name document no. japanese english sm78k series system simulator external part user open u10092j u10092e interface specifications id78k0 integrated debugger ews based reference u11151j id78k0 integrated debugger pc based reference u11539j u11539e id78k0 integrated debugger windows based guide u11649j u11649e sd78k/0 screen debugger introduction eeu-852 u10539e pc-9800 series (ms-dos) based reference u10952j sd78k/0 screen debugger introduction eeu-5024 eeu-1414 ibm pc/at (pc dos) based reference u11279j u11279e embedded software documents (users manual) document name document no. japanese english 78k/0 series real-time os fundamental u11537j u11537e installation u11536j u11536e 78k/0 series os mx78k0 fundamental u12257j fuzzy knowledge data creation tool eeu-829 eeu-1438 78k/0, 78k/ii, 87ad series eeu-862 eeu-1444 fuzzy inference development support system - translator 78k/0 series fuzzy inference development suport system - eeu-858 eeu-1441 fuzzy inference module 78k/0 series fuzzy inference development support system - eeu-921 eeu-1458 fuzzy inference debugger other documents document name document no. japanese english ic package manual c10943x semiconductor device mounting technology manual c11535j c10535e quality grades on nec semiconductor device c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e electrostatic discharge (esd) test mem-539 guide to quality assurance for semiconductor device c11893j mei-1202 guide for products related to microcomputer: other companies u11416j caution the contents of the above related documents are subject to change without notice. the latest documents should be used for designing, etc.
72 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
73 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j98. 2
74 m pd78011f, 78012f, 78013f, 78014f, 78015f, 78016f, 78018f fip and iebus are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. ibm dos, pc/at, and pc dos are trademarks of ibm corporation. hp9000 series 300, hp9000 series 700, and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. the related documents referred to in this publication may include preliminary versions. however, preliminary versions are not marked as such. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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